Regviz

stm32 /stm32wl /STM32WL5x_CM4 /TIM16 /CCMR1_Output

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CCMR1_Output

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/TIM17/CCMR1_Output#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CC1S 0 (OC1FE)OC1FE 0 (OC1PE)OC1PE 0OC1M0 (OC1M_3)OC1M_3

Description

TIM16/TIM17 capture/compare mode register 1

Fields

CC1S

CC1S
OC1FE

OC1FE
OC1PE

OC1PE
OC1M

OC1M
OC1M_3

OC1M

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32