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stm32 /stm32wl /STM32WL5x_CM4 /TIM16 /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CEN)CEN 0 (UDIS)UDIS 0 (URS)URS 0 (OPM)OPM 0 (ARPE)ARPE 0CKD0 (UIFREMAP)UIFREMAP

Description

TIM16/TIM17 control register 1

Fields

CEN

Counter enable
UDIS

Update disable
URS

Update request source
OPM

One pulse mode
ARPE

Auto-reload preload enable
CKD

Clock division
UIFREMAP

UIF status bit remapping

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32