Regviz

stm32 /stm32wl /STM32WL5x_CM4 /TIM2 /TIM2_OR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIM2_OR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM4/TIM2/TIM2_OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ETR_RMP)ETR_RMP 0TI4_RMP

Description

TIM2 option register

Fields

ETR_RMP

External trigger remap
TI4_RMP

Input capture 4 remap

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32