stm32 /stm32wl /STM32WLE5_CM4 /DMA1 /IFCR

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Interpret as IFCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GIF1)GIF1 0 (TCIF1)TCIF1 0 (HTIF1)HTIF1 0 (TEIF1)TEIF1 0 (GIF2)GIF2 0 (TCIF2)TCIF2 0 (HTIF2)HTIF2 0 (TEIF2)TEIF2 0 (GIF3)GIF3 0 (TCIF3)TCIF3 0 (HTIF3)HTIF3 0 (TEIF3)TEIF3 0 (GIF4)GIF4 0 (TCIF4)TCIF4 0 (HTIF4)HTIF4 0 (TEIF4)TEIF4 0 (GIF5)GIF5 0 (TCIF5)TCIF5 0 (HTIF5)HTIF5 0 (TEIF5)TEIF5 0 (GIF6)GIF6 0 (TCIF6)TCIF6 0 (HTIF6)HTIF6 0 (TEIF6)TEIF6 0 (GIF7)GIF7 0 (TCIF7)TCIF7 0 (HTIF7)HTIF7 0 (TEIF7)TEIF7

Description

interrupt flag clear register

Fields

GIF1

global interrupt flag clear for channel 1

TCIF1

transfer complete flag clear for channel 1

HTIF1

half transfer flag clear for channel 1

TEIF1

transfer error flag clear for channel 1

GIF2

global interrupt flag clear for channel 2

TCIF2

transfer complete flag clear for channel 2

HTIF2

half transfer flag clear for channel 2

TEIF2

transfer error flag clear for channel 2

GIF3

global interrupt flag clear for channel 3

TCIF3

transfer complete flag clear for channel 3

HTIF3

half transfer flag clear for channel 3

TEIF3

transfer error flag clear for channel 3

GIF4

global interrupt flag clear for channel 4

TCIF4

transfer complete flag clear for channel 4

HTIF4

half transfer flag clear for channel 4

TEIF4

transfer error flag clear for channel 4

GIF5

global interrupt flag clear for channel 5

TCIF5

transfer complete flag clear for channel 5

HTIF5

half transfer flag clear for channel 5

TEIF5

transfer error flag clear for channel 5

GIF6

global interrupt flag clear for channel 6

TCIF6

transfer complete flag clear for channel 6

HTIF6

half transfer flag clear for channel 6

TEIF6

transfer error flag clear for channel 6

GIF7

global interrupt flag clear for channel 7

TCIF7

transfer complete flag clear for channel 7

HTIF7

half transfer flag clear for channel 7

TEIF7

transfer error flag clear for channel 7

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