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stm32 /stm32wl /STM32WLE5_CM4 /LPTIM1 /LPTIM1_OR

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Interpret as LPTIM1_OR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OR_0)OR_0 0 (OR_1)OR_1

Description

option register

Fields

OR_0

Option register bit 0
OR_1

Option register bit 1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32