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stm32 /stm32wl /STM32WLE5_CM4 /LPTIM3 /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (SNGSTRT)SNGSTRT 0 (CNTSTRT)CNTSTRT 0 (COUNTRST)COUNTRST 0 (RSTARE)RSTARE

Description

control register

Fields

ENABLE

ENABLE
SNGSTRT

SNGSTRT
CNTSTRT

CNTSTRT
COUNTRST

COUNTRST
RSTARE

RSTARE

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32