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stm32 /stm32wl /STM32WLE5_CM4 /PKA /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BUSY)BUSY 0 (PROCENDF)PROCENDF 0 (RAMERRF)RAMERRF 0 (ADDRERRF)ADDRERRF

Description

status register

Fields

BUSY

PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started.
PROCENDF

PKA End of Operation flag
RAMERRF

PKA RAM error flag
ADDRERRF

Address error flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32