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stm32 /stm32wl /STM32WLE5_CM4 /TIM17 /DCR

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Interpret as DCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DBA0DBL

Description

TIM16/TIM17 DMA control register

Fields

DBA

DMA base address
DBL

DMA burst length

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32