Regviz

stm32 /stm32wl /STM32WLE5_CM4 /TIM17 /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/TIM17/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UIF)UIF 0 (CC1IF)CC1IF 0 (COMIF)COMIF 0 (BIF)BIF 0 (CC1OF)CC1OF

Description

TIM16/TIM17 status register

Fields

UIF

Update interrupt flag
CC1IF

Capture/Compare 1 interrupt flag
COMIF

COM interrupt flag
BIF

Break interrupt flag
CC1OF

Capture/Compare 1 overcapture flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32