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stm32 /stm32wl /STM32WLE5_CM4 /TIM17 /TIM17_OR1

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Interpret as TIM17_OR1

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM4/TIM17/TIM17_OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1_RMP

Description

TIM17 option register 1

Fields

TI1_RMP

Timer 17 input 1 connection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32