Regviz

stm32 /stm32wl /STM32WLE5_CM4 /TIM17 /TIM17_TISEL

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Interpret as TIM17_TISEL

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/TIM17/TIM17_TISEL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TISEL

Description

TIM17 input selection register

Fields

TISEL

TISEL

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32