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stm32 /stm32wl /STM32WLE5_CM4 /USART1 /RTOR

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Interpret as RTOR

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/USART1/RTOR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RTO0BLEN

Description

receiver timeout register

Fields

RTO

Receiver timeout value
BLEN

Block Length

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32