stm32 /stm32wl3 /STM32WL33 /TIM16 /BDTR

DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary

outputs. DT correspond to this duration.

DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS

DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS

DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS

DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS

Example if TDTS=125ns (8MHz), dead-time possible values are:

0 to 15875 ns by 125 ns steps,

16 us to 31750 ns by 250 ns steps,

32 us to 63 us by 1 us steps,

64 us to 126 us by 2 us steps

Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

LOCK[1:0]: Lock configuration

These bits offer a write protection against software errors.

00: LOCK OFF - No bit is write protected

01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2

register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in

TIMx_AF1 register can no longer be written.

10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER

register, as long as the related channel is configured in output through the CCxS bits) as well

as OSSR and OSSI bits can no longer be written.

11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in

TIMx_CCMRx registers, as long as the related channel is configured in output through the

CCxS bits) can no longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register

has been written, their content is frozen until the next reset.

OSSI: Off-state selection for Idle mode

This bit is used when MOE=0 on channels configured as outputs.

See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare

enable register (TIMx_CCER)).

0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)

1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or

CCxNE=1. OC/OCN enable output signal=1)

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK

bits in TIMx_BDTR register).

OSSR: Off-state selection for Run mode

This bit is used when MOE=1 on channels that have a complementary output which are

configured as outputs. OSSR is not implemented if no complementary output is implemented

in the timer.

See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare

enable register (TIMx_CCER)).

0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which

is taken over by the AFIO logic, which forces a Hi-Z state)

1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1

or CCxNE=1 (the output is still controlled by the timer).

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK

bits in TIMx_BDTR register).

BKE: Break enable

1; Break inputs (BRK) enabled

Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIMx_BDTR register).

Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break inputs (BRK) disabled

BKP: Break polarity

0: Break input BRK is active low.

1: Break input BRK is active high

Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK

bits in TIMx_BDTR register).

Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

AOE: Automatic output enable

not be active)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits

in TIMx_BDTR register).

0 (B_0x0): MOE can be set only by software

1 (B_0x1): MOE can be set by software or automatically at the next update event (if the break input is

MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as the break input is active. It is set

by software or automatically depending on the AOE bit. It is acting only on the channels

which are configured in output.

0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.

1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in

TIMx_CCER register)

See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare

enable register (TIMx_CCER)).

BKDSRM: Break Disarm

0: Break input BRK is armed

1: Break input BRK is disarmed

This bit is cleared by hardware when no break source is active.

The BKDSRM bit must be set by software to release the bidirectional output control (opendrain

output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the

fault condition has disappeared.

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

BKBID: Break Bidirectional

0: Break input BRK in input mode

1: Break input BRK in bidirectional mode

In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input

mode and in open drain output mode. Any active break event asserts a low logic level on the

Break input to indicate an internal break event to external devices.

Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits

in TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.