ARM /ARMCM3xxx /TIMER0 /CR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disable)EN 0 (Reserved)RST 0 (Count_UP)CNT0 (Continous)MODE0 (Disabled)PSC 0 (CAP_SRC)CNTSRC0 (CClk)CAPSRC0 (RISING)CAPEDGE 0 (NONE)TRGEXT 0 (RELOAD0)RELOAD 0 (KEEP)IDR0 (STOP)S

CAPEDGE=RISING, S=STOP, PSC=Disabled, CNT=Count_UP, TRGEXT=NONE, IDR=KEEP, RELOAD=RELOAD0, CAPSRC=CClk, MODE=Continous, EN=Disable, RST=Reserved, CNTSRC=CAP_SRC

Description

Control Register

Fields

EN

Enable

0 (Disable): Timer is disabled and does not operate

1 (Enable): Timer is enabled and can operate

RST

Reset Timer

0 (Reserved): Write as ZERO if necessary

1 (Reset_Timer): Reset the Timer

CNT

Counting direction

0 (Count_UP): Timer Counts UO and wraps, if no STOP condition is set

1 (Count_DOWN): Timer Counts DOWN and wraps, if no STOP condition is set

2 (Toggle): Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set

MODE

Operation Mode

0 (Continous): Timer runs continously

1 (Single_ZERO_MAX): Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops

2 (Single_MATCH): Timer counts to the Value of MATCH Register and stops

3 (Reload_ZERO_MAX): Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues

4 (Reload_MATCH): Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues

PSC

Use Prescaler

0 (Disabled): Prescaler is not used

1 (Enabled): Prescaler is used as divider

CNTSRC

Timer / Counter Source Divider

0 (CAP_SRC): Capture Source is used directly

1 (CAP_SRC_div2): Capture Source is divided by 2

2 (CAP_SRC_div4): Capture Source is divided by 4

3 (CAP_SRC_div8): Capture Source is divided by 8

4 (CAP_SRC_div16): Capture Source is divided by 16

5 (CAP_SRC_div32): Capture Source is divided by 32

6 (CAP_SRC_div64): Capture Source is divided by 64

7 (CAP_SRC_div128): Capture Source is divided by 128

8 (CAP_SRC_div256): Capture Source is divided by 256

CAPSRC

Timer / Counter Capture Source

0 (CClk): Core Clock

1 (GPIOA_0): GPIO A, PIN 0

2 (GPIOA_1): GPIO A, PIN 1

3 (GPIOA_2): GPIO A, PIN 2

4 (GPIOA_3): GPIO A, PIN 3

5 (GPIOA_4): GPIO A, PIN 4

6 (GPIOA_5): GPIO A, PIN 5

7 (GPIOA_6): GPIO A, PIN 6

8 (GPIOA_7): GPIO A, PIN 7

9 (GPIOB_0): GPIO B, PIN 0

10 (GPIOB_1): GPIO B, PIN 1

11 (GPIOB_2): GPIO B, PIN 2

12 (GPIOB_3): GPIO B, PIN 3

13 (GPIOC_0): GPIO C, PIN 0

14 (GPIOC_5): GPIO C, PIN 1

15 (GPIOC_6): GPIO C, PIN 2

CAPEDGE

Capture Edge, select which Edge should result in a counter increment or decrement

0 (RISING): Only rising edges result in a counter increment or decrement

1 (FALLING): Only falling edges result in a counter increment or decrement

2 (BOTH): Rising and falling edges result in a counter increment or decrement

TRGEXT

Triggers an other Peripheral

0 (NONE): No Trigger is emitted

1 (DMA1): DMA Controller 1 is triggered, dependant on MODE

2 (DMA2): DMA Controller 2 is triggered, dependant on MODE

3 (UART): UART is triggered, dependant on MODE

RELOAD

Select RELOAD Register n to reload Timer on condition

0 (RELOAD0): Selects Reload Register number 0

1 (RELOAD1): Selects Reload Register number 1

2 (RELOAD2): Selects Reload Register number 2

3 (RELOAD3): Selects Reload Register number 3

IDR

Selects, if Reload Register number is incremented, decremented or not modified

0 (KEEP): Reload Register number does not change automatically

1 (INCREMENT): Reload Register number is incremented on each match

2 (DECREMENT): Reload Register number is decremented on each match

S

Starts and Stops the Timer / Counter

0 (STOP): Timer / Counter is stopped

1 (START): Timer / Counter is started

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