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ARM /CMSDK_CM3 /UART0 /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disable)TXEN 0 (Disable)RXEN 0 (Disable)TXINT 0 (Disable)RXINT 0 (Disable)TXOVINT 0 (Disable)RVOVINT 0 (Disable)HSTX

TXINT=Disable, RXEN=Disable, TXEN=Disable, TXOVINT=Disable, HSTX=Disable, RVOVINT=Disable, RXINT=Disable

Description

UART Control Register

Fields

TXEN

TX Enable

0 (Disable): Disabled

1 (Enable): Enabled
RXEN

RX Enable

0 (Disable): Disabled

1 (Enable): Enabled
TXINT

TX Interrupt Enable

0 (Disable): Disabled

1 (Enable): Enabled
RXINT

RX Interrupt Enable

0 (Disable): Disabled

1 (Enable): Enabled
TXOVINT

TX Overrun Interrupt Enable

0 (Disable): Disabled

1 (Enable): Enabled
RVOVINT

RX Overrun Interrupt Enable

0 (Disable): Disabled

1 (Enable): Enabled
HSTX

High Speed Test Mode for TX only

0 (Disable): Disabled

1 (Enable): Enabled

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data