ARM /CPSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CPSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0M0 (T)T0 (F)F0 (I)I0 (A)A0 (E)E0IT0GE0 (J)J0IT0 (Q)Q0 (V)V0 (C)C0 (Z)Z0 (N)N

Description

Current Program Status Register

Fields

M

Processor mode bits

16 (User): User mode

17 (FIQ): FIQ mode

18 (IRQ): IRQ mode

19 (Supervisor): Supervisor mode

23 (Abort): Abort mode

27 (Undefined): Undefined mode

31 (System): System mode

T

Thumb execution state bit

F

FIQ mask bit

I

IRQ mask bit

A

Asynchronous abort mask bit

E

Data endianness bit

IT

If-Then execution state bits

GE

Greater than or equal flags

J

Jazelle state bit

IT

If-Then execution state bits

Q

Sticky overflow condition flag

V

Overflow condition flag

C

Carry condition flag

Z

Zero condition flag

N

Negative condition flag

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