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Allwinner /D1H /AudioCodec /AC_DAC_DRC_HKl

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Interpret as AC_DAC_DRC_HKl

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Description

DAC DRC Limiter Slope High Setting Register

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data