CE_CLK

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Interpret as CE_CLK

CLK_GATING=OFF, FACTOR_N=N1, CLK_SRC_SEL=HOSC

CE Clock Register

FACTOR_M	Factor M
FACTOR_N	Factor N 0 (N1): undefined 1 (N2): undefined 2 (N4): undefined 3 (N8): undefined
CLK_SRC_SEL	Clock Source Select 0 (HOSC): undefined 1 (PLL_PERI_2X): undefined 2 (PLL_PERI_1X): undefined
CLK_GATING	Gating Clock 0 (OFF): undefined 1 (ON): undefined

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