CLK_SRC_SEL=PLL_VIDEO0_1X, GATING=OFF
CLK27M FANOUT Register
DIV0 | Factor M |
DIV1 | Factor N |
CLK_SRC_SEL | Clock Source Select 0 (PLL_VIDEO0_1X): undefined 1 (PLL_VIDEO1_1X): undefined |
GATING | Gating for CLK27M 0 (OFF): undefined 1 (ON): undefined |