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Allwinner /D1H /CCU /CLK27M_FAN

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Interpret as CLK27M_FAN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV00DIV1 0 (PLL_VIDEO0_1X)CLK_SRC_SEL 0 (OFF)GATING

CLK_SRC_SEL=PLL_VIDEO0_1X, GATING=OFF

Description

CLK27M FANOUT Register

Fields

DIV0

Factor M
DIV1

Factor N
CLK_SRC_SEL

Clock Source Select

0 (PLL_VIDEO0_1X): undefined

1 (PLL_VIDEO1_1X): undefined
GATING

Gating for CLK27M

0 (OFF): undefined

1 (ON): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data