Allwinner /D1H /CCU /CPU_AXI_CFG

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Interpret as CPU_AXI_CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CPU_DIV1 0CPU_DIV2 0 (P1)PLL_CPU_OUT_EXT_DIVP 0 (HOSC)CPU_CLK_SEL

CPU_CLK_SEL=HOSC, PLL_CPU_OUT_EXT_DIVP=P1

Description

CPU_AXI Configuration Register

Fields

CPU_DIV1

Factor M

CPU_DIV2

Factor N

PLL_CPU_OUT_EXT_DIVP

PLL Output External Divider P

0 (P1): undefined

1 (P2): undefined

2 (P4): undefined

CPU_CLK_SEL

Clock Source Select

0 (HOSC): undefined

1 (CLK32K): undefined

2 (CLK16M_RC): undefined

3 (PLL_CPU_P): undefined

4 (PLL_PERI_1X): undefined

5 (PLL_PERI_2X): undefined

6 (PLL_PERI_800M): undefined

Links

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