CLK_SRC_SEL=PLL_PERI_2X, CLK_GATING=OFF
DI Clock Register
FACTOR_M | Factor M |
CLK_SRC_SEL | Clock Source Select 0 (PLL_PERI_2X): undefined 1 (PLL_VIDEO0_4X): undefined 2 (PLL_VIDEO1_4X): undefined 3 (PLL_AUDIO1_DIV2): undefined |
CLK_GATING | Gating Clock 0 (OFF): undefined 1 (ON): undefined |