Allwinner /D1H /CCU /DRAM_CLK

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Interpret as DRAM_CLK

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DRAM_DIV1 0 (N1)DRAM_DIV2 0 (PLL_DDR)CLK_SRC_SEL 0 (invalid)SDRCLK_UPD 0 (OFF)CLK_GATING

DRAM_DIV2=N1, CLK_GATING=OFF, CLK_SRC_SEL=PLL_DDR, SDRCLK_UPD=invalid

Description

DRAM Clock Register

Fields

DRAM_DIV1

Factor M

DRAM_DIV2

Factor N

0 (N1): undefined

1 (N2): undefined

2 (N4): undefined

3 (N8): undefined

CLK_SRC_SEL

Clock Source Select

0 (PLL_DDR): undefined

1 (PLL_AUDIO1_DIV2): undefined

2 (PLL_PERI_2X): undefined

3 (PLL_PERI_800M): undefined

SDRCLK_UPD

SDRCLK Configuration 0 Update

0 (invalid): undefined

1 (valid): undefined

CLK_GATING

Gating Clock

0 (OFF): undefined

1 (ON): undefined

Links

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