CLK_GATING=OFF, SDRCLK_UPD=invalid, DRAM_DIV2=N1, CLK_SRC_SEL=PLL_DDR
DRAM Clock Register
| DRAM_DIV1 | Factor M |
| DRAM_DIV2 | Factor N 0 (N1): undefined 1 (N2): undefined 2 (N4): undefined 3 (N8): undefined |
| CLK_SRC_SEL | Clock Source Select 0 (PLL_DDR): undefined 1 (PLL_AUDIO1_DIV2): undefined 2 (PLL_PERI_2X): undefined 3 (PLL_PERI_800M): undefined |
| SDRCLK_UPD | SDRCLK Configuration 0 Update 0 (invalid): undefined 1 (valid): undefined |
| CLK_GATING | Gating Clock 0 (OFF): undefined 1 (ON): undefined |