Allwinner /D1H /CCU /DSP_BGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSP_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)CFG_GATING 0 (Assert)RST 0 (Assert)CFG_RST 0 (Assert)DBG_RST

RST=Assert, CFG_RST=Assert, DBG_RST=Assert, CFG_GATING=Mask

Description

DSP Bus Gating Reset Register

Fields

CFG_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

CFG_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

DBG_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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