RST=Assert, DBG_RST=Assert, CFG_RST=Assert, CFG_GATING=Mask
DSP Bus Gating Reset Register
CFG_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |
CFG_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |
DBG_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |