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Allwinner /D1H /CCU /EMAC_25M_CLK

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Interpret as EMAC_25M_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Off)CLK_SRC_GATING

CLK_GATING=Off, CLK_SRC_GATING=Off

Description

EMAC_25M Clock Register

Fields

CLK_GATING

Gating Special Clock

0 (Off): undefined

1 (On): undefined
CLK_SRC_GATING

Gating the Source Clock of Special Clock

0 (Off): undefined

1 (On): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data