Allwinner /D1H /CCU /I2S0_CLK

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Interpret as I2S0_CLK

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FACTOR_M0 (N1)FACTOR_N 0 (PLL_AUDIO0_1X)CLK_SRC_SEL 0 (Off)CLK_GATING

CLK_GATING=Off, CLK_SRC_SEL=PLL_AUDIO0_1X, FACTOR_N=N1

Description

I2S Clock Register

Fields

FACTOR_M

Factor M

FACTOR_N

Factor N

0 (N1): undefined

1 (N2): undefined

2 (N4): undefined

3 (N8): undefined

CLK_SRC_SEL

Clock Source Select

0 (PLL_AUDIO0_1X): undefined

1 (PLL_AUDIO0_4X): undefined

2 (PLL_AUDIO1_DIV2): undefined

3 (PLL_AUDIO1_DIV5): undefined

CLK_GATING

Gating Clock

0 (Off): undefined

1 (On): undefined

Links

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