CLK_SRC_SEL=PLL_AUDIO0_1X, FACTOR_N=N1, CLK_GATING=Off
I2S Clock Register
| FACTOR_M | Factor M |
| FACTOR_N | Factor N 0 (N1): undefined 1 (N2): undefined 2 (N4): undefined 3 (N8): undefined |
| CLK_SRC_SEL | Clock Source Select 0 (PLL_AUDIO0_1X): undefined 1 (PLL_AUDIO0_4X): undefined 2 (PLL_AUDIO1_DIV2): undefined 3 (PLL_AUDIO1_DIV5): undefined |
| CLK_GATING | Gating Clock 0 (Off): undefined 1 (On): undefined |