Allwinner /D1H /CCU /I2S_BGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as I2S_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)I2S2_GATING 0 (Assert)I2S2_RST

I2S1_GATING=Mask, I2S0_GATING=Mask, I2S0_RST=Assert, I2S1_RST=Assert, I2S2_RST=Assert, I2S2_GATING=Mask

Description

I2S Bus Gating Reset Register

Fields

I2S1_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

I2S0_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

I2S2_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

I2S0_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

I2S1_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

I2S2_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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