Allwinner /D1H /CCU /MBUS_CLK

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MBUS_CLK

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Assert)MBUS_RST

MBUS_RST=Assert

Description

MBUS Clock Register

Fields

MBUS_RST

MBUS Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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