Regviz

Allwinner /D1H /CCU /MBUS_CLK

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Interpret as MBUS_CLK

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https://regviz.com/r/Allwinner/D1H/CCU/MBUS_CLK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Assert)MBUS_RST

MBUS_RST=Assert

Description

MBUS Clock Register

Fields

MBUS_RST

MBUS Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data