RISCV_MCLK_EN=Mask, CSI_MCLK_EN=Mask, TVIN_MCLK_EN=Mask, G2D_MCLK_EN=Mask, CE_MCLK_EN=Mask, VE_MCLK_EN=Mask, DMA_MCLK_EN=Mask
MBUS Master Clock Gating Register
| DMA_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |
| VE_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |
| CE_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |
| TVIN_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |
| CSI_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |
| G2D_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |
| RISCV_MCLK_EN | Gating MBUS Clock 0 (Mask): undefined 1 (Pass): undefined |