Allwinner /D1H /CCU /MBUS_MAT_CLK_GATING

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Interpret as MBUS_MAT_CLK_GATING

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)DMA_MCLK_EN 0 (Mask)VE_MCLK_EN 0 (Mask)CE_MCLK_EN 0 (Mask)TVIN_MCLK_EN 0 (Mask)CSI_MCLK_EN 0 (Mask)G2D_MCLK_EN 0 (Mask)RISCV_MCLK_EN

RISCV_MCLK_EN=Mask, CSI_MCLK_EN=Mask, VE_MCLK_EN=Mask, G2D_MCLK_EN=Mask, TVIN_MCLK_EN=Mask, DMA_MCLK_EN=Mask, CE_MCLK_EN=Mask

Description

MBUS Master Clock Gating Register

Fields

DMA_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

VE_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

CE_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

TVIN_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

CSI_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

G2D_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

RISCV_MCLK_EN

Gating MBUS Clock

0 (Mask): undefined

1 (Pass): undefined

Links

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