Allwinner /D1H /CCU /MSGBOX_BGR

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Interpret as MSGBOX_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)MSGBOX1_GATING 0 (Assert)MSGBOX2_RST

MSGBOX2_GATING=Mask, MSGBOX1_RST=Assert, MSGBOX0_GATING=Mask, MSGBOX0_RST=Assert, MSGBOX2_RST=Assert, MSGBOX1_GATING=Mask

Description

MSGBOX Bus Gating Reset Register

Fields

MSGBOX2_GATING

Gating Clock for CPU, DSP, RISC-V MSGBOX

0 (Mask): undefined

1 (Pass): undefined

MSGBOX0_GATING

Gating Clock for CPU, DSP, RISC-V MSGBOX

0 (Mask): undefined

1 (Pass): undefined

MSGBOX1_GATING

Gating Clock for CPU, DSP, RISC-V MSGBOX

0 (Mask): undefined

1 (Pass): undefined

MSGBOX1_RST

CPU, DSP, RISC-V MSGBOX Reset

0 (Assert): undefined

1 (Deassert): undefined

MSGBOX0_RST

CPU, DSP, RISC-V MSGBOX Reset

0 (Assert): undefined

1 (Deassert): undefined

MSGBOX2_RST

CPU, DSP, RISC-V MSGBOX Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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