Regviz

Allwinner /D1H /CCU /PCLK_FAN

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Interpret as PCLK_FAN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV0 (OFF)GATING

GATING=OFF

Description

PCLK FANOUT Register

Fields

DIV

Factor M
GATING

Gating for PCLK

0 (OFF): undefined

1 (ON): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data