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Allwinner /D1H /CCU /PLL_CPU_BIAS

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Interpret as PLL_CPU_BIAS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_CP0 (PLL_VCO_RST_IN)PLL_VCO_RST_IN

Description

PLL_CPU Bias Register

Fields

PLL_CP

PLL current bias control
PLL_VCO_RST_IN

VCO reset in

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data