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Allwinner /D1H /CCU /PLL_CPU_TUN

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Interpret as PLL_CPU_TUN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_B_OUT0 (PLL_REG_OD1)PLL_REG_OD1 0PLL_B_IN0 (PLL_REG_OD)PLL_REG_OD 0PLL_CNT_INT0PLL_VCO_GAIN 0PLL_VCO

Description

PLL_CPU Tuning Register

Fields

PLL_B_OUT

PLL-B-OUT [6:0] for verify
PLL_REG_OD1

PLL-REG-OD1 for verify
PLL_B_IN

PLL-B-IN [6:0] for verify
PLL_REG_OD

PLL-REG-OD0 for verify
PLL_CNT_INT

Counter initial control
PLL_VCO_GAIN

KVCO gain control
PLL_VCO

VCO range control

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data