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Allwinner /D1H /CCU /PLL_DDR_PAT1_CTRL

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Interpret as PLL_DDR_PAT1_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRAC_IN0 (FRAC_EN)FRAC_EN 0 (DITHER_EN)DITHER_EN

Description

PLL_DDR Pattern1 Control Register

Fields

FRAC_IN

Fraction In
FRAC_EN

Fraction Enable
DITHER_EN

Dither Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data