PLL_LOCK_FLAG_EN=Disable, CLK_SRC_SEL=PLL_CPUX
PLL Lock Debug Control Register
CLK_SRC_SEL | Clock Source Select 0 (PLL_CPUX): undefined 1 (PLL_DDR): undefined 2 (PLL_PERI_2X): undefined 3 (PLL_VIDEO0_4X): undefined 4 (PLL_VIDEO1_4X): undefined 5 (PLL_VE): undefined 6 (PLL_AUDIO0): undefined 7 (PLL_AUDIO1): undefined |
PLL_LOCK_FLAG_EN | Debug Enable 0 (Disable): undefined 1 (Enable): undefined |