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Allwinner /D1H /CCU /PLL_LOCK_DBG_CTRL

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Interpret as PLL_LOCK_DBG_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLL_CPUX)CLK_SRC_SEL 0 (Disable)PLL_LOCK_FLAG_EN

PLL_LOCK_FLAG_EN=Disable, CLK_SRC_SEL=PLL_CPUX

Description

PLL Lock Debug Control Register

Fields

CLK_SRC_SEL

Clock Source Select

0 (PLL_CPUX): undefined

1 (PLL_DDR): undefined

2 (PLL_PERI_2X): undefined

3 (PLL_VIDEO0_4X): undefined

4 (PLL_VIDEO1_4X): undefined

5 (PLL_VE): undefined

6 (PLL_AUDIO0): undefined

7 (PLL_AUDIO1): undefined
PLL_LOCK_FLAG_EN

Debug Enable

0 (Disable): undefined

1 (Enable): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data