PLL_LOCK_MDSEL=CC_24_26, PLL_EN=disable, PLL_SDM_EN=disable, PLL_LDO_EN=disable, LOCK=unlocked, LOCK_ENABLE=disable, PLL_UNLOCK_MDSEL=CC_21_29, PLL_OUTPUT_GATE=disable
PLL_VE Control Register
| PLL_OUTPUT_DIV2 | PLL Output Div M0 |
| PLL_INPUT_DIV2 | PLL Input Div M1 |
| PLL_LOCK_MDSEL | PLL Lock Level 0 (CC_24_26): undefined 1 (CC_23_27): undefined |
| PLL_UNLOCK_MDSEL | PLL Unlock Level 0 (CC_21_29): undefined 1 (CC_22_28): undefined 2 (CC_20_30): undefined |
| PLL_N | PLL N |
| PLL_SDM_EN | PLL SDM Enable 0 (disable): undefined 1 (enable): undefined |
| PLL_OUTPUT_GATE | PLL Output Gating Enable 0 (disable): undefined 1 (enable): undefined |
| LOCK | PLL Lock Status 0 (unlocked): undefined 1 (locked): undefined |
| LOCK_ENABLE | Lock Enable 0 (disable): undefined 1 (enable): undefined |
| PLL_LDO_EN | LDO Enable 0 (disable): undefined 1 (enable): undefined |
| PLL_EN | PLL Enable 0 (disable): undefined 1 (enable): undefined |