Allwinner /D1H /CCU /PLL_VE_CTRL

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Interpret as PLL_VE_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLL_OUTPUT_DIV2)PLL_OUTPUT_DIV2 0 (PLL_INPUT_DIV2)PLL_INPUT_DIV2 0 (CC_24_26)PLL_LOCK_MDSEL 0 (CC_21_29)PLL_UNLOCK_MDSEL 0PLL_N0 (disable)PLL_SDM_EN 0 (disable)PLL_OUTPUT_GATE 0 (unlocked)LOCK 0 (disable)LOCK_ENABLE 0 (disable)PLL_LDO_EN 0 (disable)PLL_EN

PLL_SDM_EN=disable, PLL_EN=disable, LOCK_ENABLE=disable, LOCK=unlocked, PLL_OUTPUT_GATE=disable, PLL_LDO_EN=disable, PLL_UNLOCK_MDSEL=CC_21_29, PLL_LOCK_MDSEL=CC_24_26

Description

PLL_VE Control Register

Fields

PLL_OUTPUT_DIV2

PLL Output Div M0

PLL_INPUT_DIV2

PLL Input Div M1

PLL_LOCK_MDSEL

PLL Lock Level

0 (CC_24_26): undefined

1 (CC_23_27): undefined

PLL_UNLOCK_MDSEL

PLL Unlock Level

0 (CC_21_29): undefined

1 (CC_22_28): undefined

2 (CC_20_30): undefined

PLL_N

PLL N

PLL_SDM_EN

PLL SDM Enable

0 (disable): undefined

1 (enable): undefined

PLL_OUTPUT_GATE

PLL Output Gating Enable

0 (disable): undefined

1 (enable): undefined

LOCK

PLL Lock Status

0 (unlocked): undefined

1 (locked): undefined

LOCK_ENABLE

Lock Enable

0 (disable): undefined

1 (enable): undefined

PLL_LDO_EN

LDO Enable

0 (disable): undefined

1 (enable): undefined

PLL_EN

PLL Enable

0 (disable): undefined

1 (enable): undefined

Links

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