Allwinner /D1H /CCU /RISCV_CLK

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Interpret as RISCV_CLK

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV_CFG0AXI_DIV_CFG 0 (HOSC)CLK_SRC_SEL

CLK_SRC_SEL=HOSC

Description

RISC-V Clock Register

Fields

DIV_CFG

Factor M

AXI_DIV_CFG

Factor N

CLK_SRC_SEL

Clock Source Select

0 (HOSC): undefined

1 (CLK32K): undefined

2 (CLK16M_RC): undefined

3 (PLL_PERI_800M): undefined

4 (PLL_PERI_1X): undefined

5 (PLL_CPU): undefined

6 (PLL_AUDIO1_DIV2): undefined

Links

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