Allwinner /D1H /CCU /SMHC_BGR

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Interpret as SMHC_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)SMHC2_GATING 0 (Assert)SMHC0_RST

SMHC0_GATING=Mask, SMHC2_RST=Assert, SMHC1_RST=Assert, SMHC1_GATING=Mask, SMHC0_RST=Assert, SMHC2_GATING=Mask

Description

SMHC Bus Gating Reset Register

Fields

SMHC0_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

SMHC1_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

SMHC2_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

SMHC2_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

SMHC1_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

SMHC0_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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