SPI0_RST=Assert, SPI1_GATING=Mask, SPI0_GATING=Mask, SPI1_RST=Assert
SPI Bus Gating Reset Register
SPI1_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
SPI0_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
SPI0_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |
SPI1_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |