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Allwinner /D1H /CCU /SPI_BGR

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Interpret as SPI_BGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)SPI0_GATING 0 (Assert)SPI1_RST

SPI0_RST=Assert, SPI1_GATING=Mask, SPI0_GATING=Mask, SPI1_RST=Assert

Description

SPI Bus Gating Reset Register

Fields

SPI1_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined
SPI0_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined
SPI0_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined
SPI1_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data