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Allwinner /D1H /CCU /TPADC_CLK

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Interpret as TPADC_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HOSC)CLK_SRC_SEL 0 (Off)CLK_GATING

CLK_GATING=Off, CLK_SRC_SEL=HOSC

Description

TPADC Clock Register

Fields

CLK_SRC_SEL

Clock Source Select

0 (HOSC): undefined

1 (PLL_AUDIO0_1X): undefined
CLK_GATING

Gating Clock

0 (Off): undefined

1 (On): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data