Allwinner /D1H /CCU /TVD_BGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TVD_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)TOP_GATING 0 (Mask)GATING 0 (Assert)TOP_RST 0 (Assert)RST

RST=Assert, TOP_RST=Assert, TOP_GATING=Mask, GATING=Mask

Description

TVD Bus Gating Reset Register

Fields

TOP_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

TOP_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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