Allwinner /D1H /CCU /TWI_BGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TWI_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)TWI1_GATING 0 (Assert)TWI0_RST

TWI3_RST=Assert, TWI0_GATING=Mask, TWI2_GATING=Mask, TWI2_RST=Assert, TWI3_GATING=Mask, TWI1_RST=Assert, TWI1_GATING=Mask, TWI0_RST=Assert

Description

TWI Bus Gating Reset Register

Fields

TWI0_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

TWI2_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

TWI3_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

TWI1_GATING

Gating Clock

0 (Mask): undefined

1 (Pass): undefined

TWI3_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

TWI2_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

TWI1_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

TWI0_RST

Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

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