TWI0_RST=Assert, TWI1_RST=Assert, TWI1_GATING=Mask, TWI3_GATING=Mask, TWI2_GATING=Mask, TWI2_RST=Assert, TWI0_GATING=Mask, TWI3_RST=Assert
TWI Bus Gating Reset Register
| TWI1_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
| TWI3_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
| TWI2_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
| TWI0_GATING | Gating Clock 0 (Mask): undefined 1 (Pass): undefined |
| TWI0_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |
| TWI1_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |
| TWI2_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |
| TWI3_RST | Reset 0 (Assert): undefined 1 (Deassert): undefined |