UART_BGR

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Interpret as UART_BGR

UART5_GATING=Mask, UART4_RST=Assert, UART3_GATING=Mask, UART0_GATING=Mask, UART1_RST=Assert, UART0_RST=Assert, UART2_RST=Assert, UART1_GATING=Mask, UART4_GATING=Mask, UART2_GATING=Mask, UART3_RST=Assert, UART5_RST=Assert

Description

UART Bus Gating Reset Register

Fields

UART5_GATING	Gating Clock 0 (Mask): undefined 1 (Pass): undefined
UART3_GATING	Gating Clock 0 (Mask): undefined 1 (Pass): undefined
UART0_GATING	Gating Clock 0 (Mask): undefined 1 (Pass): undefined
UART1_GATING	Gating Clock 0 (Mask): undefined 1 (Pass): undefined
UART4_GATING	Gating Clock 0 (Mask): undefined 1 (Pass): undefined
UART2_GATING	Gating Clock 0 (Mask): undefined 1 (Pass): undefined
UART4_RST	Reset 0 (Assert): undefined 1 (Deassert): undefined
UART1_RST	Reset 0 (Assert): undefined 1 (Deassert): undefined
UART0_RST	Reset 0 (Assert): undefined 1 (Deassert): undefined
UART2_RST	Reset 0 (Assert): undefined 1 (Deassert): undefined
UART3_RST	Reset 0 (Assert): undefined 1 (Deassert): undefined
UART5_RST	Reset 0 (Assert): undefined 1 (Deassert): undefined

Links

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