Regviz

Allwinner /D1H /CCU /USB0_CLK

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Interpret as USB0_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIV_48M)CLK12M_SEL 0 (Assert)RSTN 0 (Off)CLKEN

CLK12M_SEL=DIV_48M, CLKEN=Off, RSTN=Assert

Description

USB0 Clock Register

Fields

CLK12M_SEL

OHCI 12M Source Select

0 (DIV_48M): undefined

1 (DIV_24M): undefined

2 (RTC_32K): undefined
RSTN

PHY Reset

0 (Assert): undefined

1 (Deassert): undefined
CLKEN

Gating Special Clock

0 (Off): undefined

1 (On): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data