CLK12M_SEL=DIV_48M, CLKEN=Off, RSTN=Assert
USB1 Clock Register
CLK12M_SEL | OHCI 12M Source Select 0 (DIV_48M): undefined 1 (DIV_24M): undefined 2 (RTC_32K): undefined |
RSTN | PHY Reset 0 (Assert): undefined 1 (Deassert): undefined |
CLKEN | Gating Special Clock 0 (Off): undefined 1 (On): undefined |