Allwinner /D1H /CCU /USB_BGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as USB_BGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Mask)USBOHCI1_GATING 0 (Mask)USBEHCI1_GATING 0 (Mask)USBOTG0_GATING 0 (Assert)USBOHCI0_RST 0 (Assert)USBEHCI1_RST 0 (Assert)USBOTG0_RST

USBEHCI0_RST=Assert, USBEHCI0_GATING=Mask, USBOHCI0_GATING=Mask, USBEHCI1_RST=Assert, USBOHCI1_GATING=Mask, USBOTG0_GATING=Mask, USBEHCI1_GATING=Mask, USBOTG0_RST=Assert, USBOHCI1_RST=Assert, USBOHCI0_RST=Assert

Description

USB Bus Gating Reset Register

Fields

USBOHCI0_GATING

USBOHCI Gating Clock

0 (Mask): undefined

1 (Pass): undefined

USBOHCI1_GATING

USBOHCI Gating Clock

0 (Mask): undefined

1 (Pass): undefined

USBEHCI0_GATING

USBEHCI Gating Clock

0 (Mask): undefined

1 (Pass): undefined

USBEHCI1_GATING

USBEHCI Gating Clock

0 (Mask): undefined

1 (Pass): undefined

USBOTG0_GATING

USBOTG0 Gating Clock

0 (Mask): undefined

1 (Pass): undefined

USBOHCI1_RST

USBOHCI Reset

0 (Assert): undefined

1 (Deassert): undefined

USBOHCI0_RST

USBOHCI Reset

0 (Assert): undefined

1 (Deassert): undefined

USBEHCI0_RST

USBEHCI Reset

0 (Assert): undefined

1 (Deassert): undefined

USBEHCI1_RST

USBEHCI Reset

0 (Assert): undefined

1 (Deassert): undefined

USBOTG0_RST

USBOTG0 Reset

0 (Assert): undefined

1 (Deassert): undefined

Links

()