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Allwinner /D1H /CCU /VE_CLK

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Interpret as VE_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FACTOR_M0 (VEPLL)CLK_SRC_SEL 0 (OFF)CLK_GATING

CLK_SRC_SEL=VEPLL, CLK_GATING=OFF

Description

VE Clock Register

Fields

FACTOR_M

Factor M
CLK_SRC_SEL

Clock Source Select

0 (VEPLL): undefined

1 (PLL_PERI_2X): undefined
CLK_GATING

Gating Clock

0 (OFF): undefined

1 (ON): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data