Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Allwinner/D1H/CCU/VE_CLK#0x0
CLK_GATING=OFF, CLK_SRC_SEL=VEPLL
VE Clock Register
Factor M
Clock Source Select
0 (VEPLL): undefined
1 (PLL_PERI_2X): undefined
Gating Clock
0 (OFF): undefined
1 (ON): undefined
https://github.com/cmsis-svd/cmsis-svd-data