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Allwinner /D1H /CSIC /CSIC_DMA1 /CSIC_DMA_VI_TO_TH1_REG

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Interpret as CSIC_DMA_VI_TO_TH1_REG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Description

CSIC DMA Video Input Timeout Threshold1 Register

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data