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Allwinner /D1H /EMAC /EMAC_BASIC_CTL1

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Interpret as EMAC_BASIC_CTL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (no_valid)SOFT_RST 0 (Same)RX_TX_PRI 0BURST_LEN

RX_TX_PRI=Same, SOFT_RST=no_valid

Description

EMAC Basic Control Register1

Fields

SOFT_RST

Soft Reset all Registers and Logic

0 (no_valid): undefined

1 (reset): undefined
RX_TX_PRI

RX TX DMA Priority

0 (Same): undefined

1 (RoT): undefined
BURST_LEN

The burst length of RX and TX DMA transfer

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data