EMAC_INT_EN

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Interpret as EMAC_INT_EN

TX_EARLY_INT_EN=Disable, TX_DMA_STOPPED_INT_EN=Disable, TX_INT_EN=Disable, TX_TIMEOUT_INT_EN=Disable, RX_INT_EN=Disable, TX_BUF_UA_INT_EN=Disable, TX_UNDERFLOW_INT_EN=Disable, RX_TIMEOUT_INT_EN=Disable, RX_EARLY_INT_EN=Disable, RX_DMA_STOPPED_INT_EN=Disable, RX_BUF_UA_INT_EN=Disable, RX_OVERFLOW_INT_EN=Disable

Description

EMAC Interrupt Enable Register

Fields

TX_INT_EN	Transmit Interrupt 0 (Disable): undefined 1 (Enable): undefined
TX_DMA_STOPPED_INT_EN	Transmit DMA FSM Stopped Interrupt 0 (Disable): undefined 1 (Enable): undefined
TX_BUF_UA_INT_EN	Transmit Buffer Available Interrupt 0 (Disable): undefined 1 (Enable): undefined
TX_TIMEOUT_INT_EN	Transmit Timeout Interrupt 0 (Disable): undefined 1 (Enable): undefined
TX_UNDERFLOW_INT_EN	Transmit Underflow Interrupt 0 (Disable): undefined 1 (Enable): undefined
TX_EARLY_INT_EN	Early Transmit Interrupt 0 (Disable): undefined 1 (Enable): undefined
RX_INT_EN	Receive Interrupt 0 (Disable): undefined 1 (Enable): undefined
RX_BUF_UA_INT_EN	Receive Buffer Unavailable Interrupt 0 (Disable): undefined 1 (Enable): undefined
RX_DMA_STOPPED_INT_EN	Receive DMA FSM Stopped Interrupt 0 (Disable): undefined 1 (Enable): undefined
RX_TIMEOUT_INT_EN	Receive Timeout Interrupt 0 (Disable): undefined 1 (Enable): undefined
RX_OVERFLOW_INT_EN	Receive Overflow Interrupt 0 (Disable): undefined 1 (Enable): undefined
RX_EARLY_INT_EN	Early Receive Interrupt 0 (Disable): undefined 1 (Enable): undefined

Links

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